1. Field of the Invention
The subject matter of the present invention is a multilayer structure, comprising a substrate and a layer of silicon and germanium (SiGe layer) deposited heteroepitaxially thereon and having a lattice constant which differs from a lattice constant of the substrate. Silicon which is deposited on a SiGe layer of this type is biaxially strained. Since the mobility of charge carriers in strained silicon is higher than in unstrained silicon, electronic components which make use of strained silicon to increase the switching speed are receiving more and more interest.
2. Description of the Related Art
In particular an SiGe layer, which consists of a mixture of silicon and germanium with a germanium content of from 20 to 50% and is as far as possible completely relaxed, is suitable for the deposition of strained silicon. Since the lattice constant of the SiGe layer is greater than that of silicon, the silicon lattice which is deposited on a layer of this type is widened, producing a layer of strained silicon.
In general, silicon is also used as a substrate for the relaxed SiGe layer to be deposited on. On account of the different lattice constants, a heteroepitaxial layer which grows is initially strained itself. The strain disappears beyond a critical layer thickness, forming dislocations. Misfit dislocations tend to continue in a plane along the direction of growth of the growing layer. However, threading dislocations are also formed as extensions of misfit dislocations. These threading dislocations extend in the direction of growth of the SiGe layer and reach as far as the surface of this layer. This occurs to an increased extent if the deposited SiGe layer is relaxed during a simple heat treatment (anneal). Threading dislocations should be avoided wherever possible, since they usually continue in layers which are deposited on the SiGe layer and disrupt the functioning of electronic components which are integrated in layers of this type. Pile-ups of threading dislocations are particularly harmful. Another important parameter for the quality of the SiGe layer is the roughness of the surface, which should be as low as possible. Misfit dislocations produce stress fields and lead to local differences in the growth rate during the growth of the SiGe layer, and ultimately to a surface topography, known as “cross-hatch” topography, which is likewise transferred to layers deposited on the SiGe layer. A measure of this cross-hatch is the RMS roughness of the surface, measured for example by AFM (Atomic Force Microscopy).
Strategies have already been developed for reducing the density of threading dislocations. One possible option is to increase the concentration of germanium in the SiGe layer in steps or continuously. Another approach pursues the objective of depositing the SiGe layer on a layer which has a high concentration of point defects. Misfit dislocations then tend to form closed dislocation loops, which lead through the area with the high concentration of point defects, rather than to lengthen into threading dislocations directed toward the surface of the SiGe layer. The density of the threading dislocations which still reach the surface of the substrate is of the order of magnitude of at least 1·107 threading dislocations/cm2 and is therefore still far too high for the material to be suitable for the fabrication of electronic components. US2004/0067644 A1 has described a process which allows the density of threading dislocations to be reduced to below 1·105 threading dislocations/cm2. The process substantially comprises etching the surface of the SiGe layer at the same time as the heat treatment which relaxes the SiGe layer (etch anneal process). An advantageous side-effect of so doing is that the surface roughness also decreases.